The present invention relates to a magnetic disk system, and particularly to a waveform equalizer therefor which includes a transversal circuit or programmable filter for implementing an optimal waveform shaping process for arbitrary data transfer rates on a read channel, thereby improving a reproduction margin.
A method of increasing the storage capacity of a magnetic disk is to increase the recording bit density. However, the conventional magnetic disk system is designed to read and write data at the same data transfer rate regardless of the track position on the disk which turns at a constant rotational speed, and therefore the recording bit density is smaller the further out as the track position is and this recording scheme is disadvantageous for the disk to have an increased storage capacity although it has a better margin of recording performance. With the intention of overcoming this problem, there has been a new recording scheme called "CDR" (Constant Density Recording). This recording scheme is designed to vary the data transfer rate depending on the track position on the disk so that outer tracks have a bit density as high as inner tracks, thereby increasing the recording capacity of the magnetic disk. Accordingly, in the CDR system, data read out of the disk has different frequency components depending on a track position, and therefore it is necessary for a waveform shaping circuit which processes the readout signal to vary its characteristics depending on the data transfer rate. When a transversal circuit is used, there arises the necessity of a waveform equalizing circuit which implements the optimal waveform equalization by varying the delay time depending on the data transfer rate. Another necessity is a programmable filter having its cutoff frequency set arbitrarily.
A cosine equalizing circuit, which is a conventional waveform equalizing circuit based on variable delay circuits, will be explained with reference to FIG. 1. The circuit consists of registers 101 and 1401, an external control signal generating circuit 1402, a frequency synthesizer 102, and a transversal circuit 104. The transversal circuit 104 consists of variable delay circuits 111-114, amplifiers 105-109, and an adder 115.
In the magnetic disk system, the register 101 stores a value determined from the data transfer rate, and the frequency synthesizer 102 produces a write clock signal 110 having a frequency which depends on the value in the register 101. For setting the delay time of the transversal circuit 104 by the register 1401, the external control signal generating circuit 1402 produces a control signal in correspondence to the value stored in the register 1401, and the control signal controls the delay time of the transversal circuit 104.
FIGS. 2a-2c shows the principle of the above-mentioned operation. The delay circuits and amplifiers produce output signals as shown by, 2302 and 2303 from an input signal 2301 depending on each delay time and amplification. These output signals are summed by the adder 115, resulting in an equalized signal shown by 2304.
A conventional programmable filter will be explained with reference to FIG. 3 and FIG. 4. FIG. 3 is a brief block diagram of a conventional programmable filter, and it consists of a register B 2101, a register A 101, a DAC (D/A converter) 2103, a programmable filter 1601, and a frequency synthesizer 102. In the magnetic disk system, the register A 101 stores a value determined from the data transfer rate, and frequency synthesizer 102 produces a write clock signal 110 with a frequency which depends on the value stored in the register A 101.
For setting the cutoff frequency of the programmable filter 1601 by the register B 2101, the D/A converter 2103 produces a control signal 1602 which corresponds to the value stored in the register B 2101, and the control signal 1602 controls the cutoff frequency of the filter.
FIG. 4 shows another conventional programmable filter which is derived from the one shown in FIG. 3 by adding a reference oscillator 2201. The D/A converter 2103 produces a control signal 1602 in response to the value stored in the register B 2101 and to the output signal of the reference oscillator 2201, and the control signal controls the cutoff frequency of the filter 1601 thereby to compensate for the dispersion of a capacitor which constitutes the filter.
FIG. 5 shows an example of the programmable filter 1601, and it consists of a low-pass filter 2401, a high-pass filter 2402, an adder 2403, and another low-pass filter 2404. The filters 2401, 2402 and 2404 are controlled by the control signal 1602. Signals similar to the signals 2302 and 2303 shown in FIG. 2b are produced from an input signal similar to the signal shown in FIG. 2a and are summed by the adder 2403 to produce an equalized signal similar to the signal 2304 shown in FIG. 2c such that the. input signal is equalized.
Conventional techniques pertinent to waveform equalizers are described in U.S. Pat. No. 4,945,311, Japanese Patent Laid-open Nos. 1-80116, 1-80117, 63-122061, and 62-102481.
In the transversal circuit arranged as described above, the delay circuit has a dispersion of delay time due to the dispersion of resistance and capacitance of the circuit elements resulting from an integrated circuit fabricating process. Moreover, in the conventional circuit arrangement, a microprocessor (MPU) stores a value in the register for the frequency synthesizer in response to a certain data transfer rate and further stores a value in the register for the delay circuit, resulting in a significant overhead process for the MPU.
In the conventional programmable filter, a microprocessor (MPU) stores a value in the register for the frequency synthesizer and further stores a value in the register for the filter cutoff frequency, resulting in a significant overhead process for the MPU. The need for two independent registers and a DAC results in the whole system having a large circuit scale. PG,7